1. Field of the Invention
The present invention relates to digital clock synchronization, and more particularly to the simultaneous synchronization of multiple redundant oscillators, and to the control and selection thereof.
2. Description of the Prior Art
Digital systems requiring a digital clock signal can typically be categorized as "asynchronous" or "synchronous" systems. An asynchronous system often does not require simultaneous clocking of its circuitry, but rather use control circuitry or "handshake" lines to control timing, and activity can occur at any time as long as no activity overlap occurs. Asynchronous systems that do utilize simultaneous clock signals do not control the data arrival time at the clocked circuit loads relative to the occurrence of clock pulses. On the other hand, a synchronous system is one where circuitry must be activated at a specific time in relation to a system clock. Synchronous systems are digital systems where the operations are typically controlled by continuous, periodic clock pulses.
In synchronous systems, it is important that activity within a circuit occurs at a particular time in relation to the clock signal. Clock skew, which can be broadly defined as phase differences due to clock path delay variations, can adversely affect the timing of activity within different areas of a circuit. Therefore, eliminating clock skew is an important issue in a synchronous design, since it is important that the driving clock signals occur simultaneously at the clock receiving circuitry in order to minimize the time that logic activity must be suspended to ensure valid clocking. Ideally, the clocking signals would occur at the same instant at all of the logic circuits requiring clock signals.
Eliminating clock skew may not be the only reason to utilize synchronized clock signals. The present invention achieves the synchronization of two independently driven synchronous sub-systems with redundant circuit loads. This invention has the advantage that the clock in either sub-system can fail due to a power failure or the failure of its source oscillators, and the load redundancy will allow the total system to continue operating. To achieve this result, both sub-systems must contain identical data and perform identical functions simultaneously. This invention synchronizes the sub-system source oscillators such that a failure of the coupling mechanism itself will not cause both sub-systems to fail.
Many of the existing clock synchronization circuits address the clock skew problem. It is known to use synchronizing circuits to synchronize a local system clock with a reference clock. Such a circuit is disclosed in U.S. Pat. No. 5,036,528, by Costantino et al., issued Jul. 30, 1991. In the Costantino circuit, a plurality of replicas of a free-running clock are generated, with each replica slightly shifted in phase from one another. An iterative process is then performed, which selects the replica which is closest to being synchronized with the reference clock. This type of synchronization results in a single system clock which is synchronized with a single reference clock. Another such circuit is disclosed in U.S. Pat. No. 4,216,544, by Boleda et al., issued Aug. 5, 1980. This circuit also synchronizes an incoming signal with a reference clock.
The present invention differs from the Costantino and Boleda concepts in that any of a plurality of oscillators may be the system clock itself. In the Costantino design, the reference clock is not used as a system clock, but is only used as a reference to generate another clock. Therefore if either the system clock or the reference clock fail, all synchronization is lost. In the present invention, multiple oscillators are synchronized with each other in pairs. The synchronization is necessary so that each of the synchronized oscillators in a synchronized clock pair can clock independent circuit loads at precisely the same time. Each of these pairs of synchronized clock signals can be independently selected to be the system clock, and if an oscillator fails, another pair of synchronized oscillators can quickly be selected to drive the system. Since synchronization amongst the oscillators themselves is the important factor, no reference clock is needed.
In U.S. Pat. No. 5,062,124, by Hayashi et al., issued Oct. 29, 1991, the design provides a clock to multiple circuit loads in a communications system. A master clock is synchronized with a reference clock, and this master clock is then distributed throughout each of the circuit loads. Although this circuit does provide a synchronized clock to multiple circuit loads, the concept varies considerably from the present invention. The Hayashi invention, like the Costantino and Boleda inventions, is still based on a single driving clock synchronized with a single reference clock. The present invention does not rely on the operation of any single oscillator. Any of the redundant oscillators may be synchronized with any of the other redundant oscillators to provide synchronized clock signals to the recipient circuitry.
One practical application of the present invention is to simultaneously clock two redundant circuit loads. This design will provide two synchronized clock signals, one to each of the circuit loads. Since the two clock signals are synchronized with each other, both circuit loads will be clocked at the same time. If one or both of the clock signals which are clocking the circuit loads were to fail, a redundant oscillator or even a redundant pair of oscillators can be quickly selected to continue to simultaneously clock the circuit loads. This results in a very efficient fault tolerant synchronization system. This will solve problems of total system failure upon the loss of a driving oscillator, or even upon loss of multiple oscillators.
An important aspect of the present invention is the simultaneous synchronization of a predetermined number of pairs of oscillators. Rather than wait until an oscillator has failed to select and synchronize a new oscillator to drive the circuit loads, the present invention constantly synchronizes a predetermined number of oscillator pairs. This provides a plurality of pre-synchronized clock pairs which can be automatically (or manually) selected very quickly upon an oscillator failure in order to maintain a continuous clock signal at the circuit loads.